In typical trellis-based detection arrangements, when a 16-state intersymbol interference (ISI) channel is combined with a single bit parity code, the number of states in the combined trellis is 32. The minimum-distance error-events in the combined trellis consist of either a single even parity error-event (i.e., +−, +−+−, +0+, . . . ) or two odd-parity error events (i.e., +, +−+, +0+0+, . . . ). Since the two odd parity error-events do not have to be close to each other, the path memory for the 32-state trellis must be longer than the parity-code block length, which is typically very large.
For example, if the parity-code block length for a channel is 82 bits, a path-memory length of L=97 is currently required. A standard 32-state shift register exchange algorithm contains 32·(L-1) flip-flops. If, e.g. the number of flip-flops is 3072, this means that the path memory alone is more than 17 times larger than the path memory for typical read channel with 16-states and L=12.
An example of a parity-sensitive Viterbi detector is disclosed and discussed in detail in U.S. Pat. No. 6,662,338, which is incorporated by reference.
In view of the foregoing, the need exists for trellis detector arrangements of reduced complexity wherein reduction in complexity does not adversely affect the performance level.